1. Technical Field
The present invention relates generally to semiconductor device testing, and more particularly, to methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure.
2. Related Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride layers. For example, a tensile-stressed silicon nitride layer may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride layer may be used to cause compression in a PFET channel. In some instances, dual stressed layers may be used, and in others a single stressed layer may be used. In any event, the stressed layer(s) modulate on-off current (Ion-Ioff) performance.
In order to achieve the benefits of the above-described technology, correct characterization of mechanical stress under a device is very important. Conventionally, inline blanket wafer stress characterization through physical bending is used. However, this approach cannot accurately reflect the mechanical stress under a transistor channel.
In view of the foregoing, there is a need in the art for a solution to provide for improved mechanical stress characterization.